Abstract
Heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a first set of one or more physical processor cores having first processing characteristics; a second set of one or more physical processor cores having second processing characteristics different from the first processing characteristics; virtual-to-physical (V-P) mapping logic to expose a plurality of virtual processors to software, the plurality of virtual processors to appear to the software as a plurality of homogeneous processor cores, the software to allocate threads to the virtual processors as if the virtual processors were homogeneous processor cores; wherein the V-P mapping logic is to map each virtual processor to a physical processor within the first set of physical processor cores or the second set of physical processor cores such that a thread allocated to a first virtual processor by software is executed by a physical processor mapped to the first virtual processor from the first set or the second set of physical processors.
Inventors
- Paolo Narvaez
- Ganapati N. Srinivasa
- Eugene Gorbatov
- Dheeraj R. Subbareddy
- Mishali Naik
- Alon Naveh
- Abirami Prabhakaran
- Eliezer Weissmann
- David A. Koufaty
- Paul Brett
- Scott D. Hahn
- Andrew J. Herdrich
- Ravishankar Iyer
- Nagabhushan Chitlur
- Inder M. Sodhi
- Gaurav Khanna
- Russell J. Fenger