Abstract
A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.
Inventors
- Paolo Narvaez
- Ganapati N. Srinivasa
- Eugene Gorbatov
- Dheeraj R. Subbareddy
- Mishali Naik
- Alon Naveh
- Abirami Prabhakaran
- Eliezer Weissmann
- David A. Koufaty
- Paul Brett
- Scott D. Hahn
- Andrew J. Herdrich
- Ravishankar Iyer
- Nagabhushan Chitlur
- Inder M. Sodhi
- Gaurav Khanna
- Russell J. Fenger