Abstract
A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.
Inventors
- Paolo Narvaez
- Ganapati N. Srinivasa
- Eugene Gorbatov
- Dheeraj R. Subbareddy
- Mishali Naik
- Alon Naveh
- Abirami Prabhakaran
- Eliezer Weissmann
- David A. Koufaty
- Paul Brett
- Scott D. Hahn
- Andrew J. Herdrich
- Gaurav Khanna
- Russell J. Fenger
- Bryant E. Bigbee
- Andrew D. Henroid