Abstract
According to one embodiment, a processor includes a plurality of processor cores for executing a plurality of threads, a shared storage communicatively coupled to the plurality of processor cores, a power control unit (PCU) communicatively coupled to the plurality of processors to determine, without any software (SW) intervention, if a thread being performed by a first processor core should be migrated to a second processor core, and a migration unit, in response to receiving an instruction from the PCU to migrate the thread, to store at least a portion of architectural state of the first processor core in the shared storage and to migrate the thread to the second processor core, without any SW intervention, such that the second processor core can continue executing the thread based on the architectural state from the shared storage without knowledge of the SW.
Inventors
- Mishali NaikGanapati N.
- SrinivasaAlon NavehInder M.
- SodhiPaolo Narvaez
- Eugene Gorbatov
- Eliezer Weissmann
- Andrew D. Henroid
- Andrew J. Herdrich
- Guarav Khanna
- Scott D. Hahn
- Paul Brett
- David A. Koufaty
- Dheeraj R. Subbareddy
- Abirami Prabhakaran